dual J-K flip-flop

The 74LS112 is a dual J-K flip-flop with preset and clear inputs, housed in a DIP-14 package. It is perfect for state control, timing circuits, and synchronous logic, offering high-speed performance, low power consumption, and manual initialization of flip-flops in digital systems.

dual J-K flip-flop

74LS76 / 7476 DIP Dual J-K Flip-Flop with Preset And Clear

74LS76 / 7476 DIP Dual J-K Flip-Flop with Preset And Clear

74LS107 DIP Dual J-K Flip-Flop with Clear

74LS107 DIP Dual J-K Flip-Flop with Clear

74LS78 DIP Dual Negative Edge Triggered J-K Flip-Flop with Preset, Common Clock & Common Clear

74LS78 DIP Dual Negative Edge Triggered J-K Flip-Flop with Preset, Common Clock & Common Clear

74HC73 DIP Dual J-K Flip-Flop With Clear

74HC73 DIP Dual J-K Flip-Flop With Clear

74LS112 DIP Dual J-K Flip-Flop with Preset and Clear

74LS112 DIP Dual J-K Flip-Flop with Preset and Clear

74LS114 DIP Dual J-K Negative-Edge-Triggered Flip-Flops

74LS114 DIP Dual J-K Negative-Edge-Triggered Flip-Flops

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